I'm a rising 5th year Electrical Engineering PhD student at Stanford University advised by Dr. Clark Barrett. I research Satisfiability Modulo Theory (SMT) based approaches to various problems in the hardware design domain. As of now, my primary focus is formal hardware verification. I also have some experience and interest in Control Theory, Machine Learning and Optimization. More generally, I'm interested in safe and reliable automation, whether that be automated design approaches or autonomous systems. I received a B.S. in Systems Science and Engineering from Washington University in St. Louis and a M.S. in Electrical Engineering from Stanford University.